1. Field of the Invention
The present invention relates to methods of fabricating semiconductor devices using oxide semiconductors. More specifically, the present invention relates to methods of fabricating field-effect transistors (FETs) using oxide semiconductors as channels.
2. Description of the Related Art
Recently, transistors having channel layers formed of transparent films have been developed by using electrically conductive oxide thin films. For example, a thin-film transistor (TFT) using a channel layer formed of a transparent conductive oxide polycrystalline thin film containing ZnO as the main component is disclosed in Japanese Patent Laid-Open No. 2002-76356. The above-mentioned thin film can be formed at a low temperature and is transparent to visible light. Therefore, a flexible transparent TFT can be fabricated on a substrate such as a plastic sheet or film.
As disclosed in the First Embodiment of Japanese Patent Laid-Open No. 2002-76356, a drain and a source of an oxide TFT are usually formed of a transparent conductive material, a metal, or a highly doped semiconductor which is different from that of an oxide-semiconductor channel layer. The drain and the source are formed on the top or bottom face of the oxide-semiconductor channel. As an example of such structures, FIG. 8 shows a structure of an inverted-staggered (bottom-gate) TFT.
With reference to FIG. 8, a TFT is configured with a substrate 81, a gate electrode 82 disposed on the substrate 81, a gate-insulating film 83 disposed on the gate electrode 82, a channel layer 84 of an oxide semiconductor disposed on the gate-insulating film 83, and a drain 85 and a source 86 disposed on the channel layer 84. The drain 85 and the source 86 are formed of a metal, a conductive oxide, or a highly doped semiconductor.
The transistor operation of the TFT is performed by applying a voltage to the gate electrode 82 to accumulate or deplete charge at the interface between the gate-insulating film 83 and the channel layer 84 and thereby to change the current value between the drain 85 and the source 86. In this TFT, the drain 85 and the source 86 are disposed on one side of the channel layer 84, and the gate-insulating film 83 is disposed on the other side of the channel layer 84. In other words, the drain 85 and the channel layer 84 are not directly connected to the effective current path for the transistor operation, i.e., the interface between the gate-insulating film 83 and the channel layer 84. Therefore, when a current flows between the drain 85 and the source 86 through the interface between the gate-insulating film 83 and the channel layer 84, the current must flow disadvantageously through unnecessary resistance.
FIG. 9 shows a structure of a staggered (top-gate) TFT.
With reference to FIG. 9, a TFT is configured with a substrate 91, a channel layer 94 disposed on the substrate 91, a drain 95 and a source 96 formed of a metal, a conductive oxide, or a highly doped semiconductor disposed on the channel layer 94, a gate-insulating film 93 disposed so as to bridge the gap between the drain 95 and the source 96, and a gate electrode 92 disposed on the gate-insulating film 93.
The transistor operation of this TFT is similarly performed by applying a voltage to the gate electrode 92 to accumulate or deplete charge at the interface between the gate-insulating film 93 and the channel layer 94 and thereby to change the current value between the drain 95 and the source 96. In a structure with microscopic asperities as in this structure, it is very difficult to completely fill the gap and difference in level between the drain 95 and the source 96 with the gate-insulating film 93. Thus, gaps unavoidably occur near the drain 95 and the source 96, as shown in FIG. 9. Therefore, the interface between the channel layer 94 and the gate-insulating film 93 is not flat, thereby forming a structure with curvature or inequalities which is a factor in degradation of the interface properties.
In addition, if the drain 95 and the source 96 are formed into appropriate shapes by etching, the etching liquid, etching gas, or plasma corrodes the surface of the channel layer 94. If they are processed by lift-off, a resist and an organic solvent pollute the surface of the channel layer 94. Therefore, the interface between the channel layer 94 and the gate-insulating film 93 cannot be maintained at favorable conditions, and thereby the characteristics of the thin-film transistor are degraded, which is a problem.
In order to solve such problems, transistors are desired to have a structure described in the fourth embodiment in Japanese Patent Laid-Open No. 2002-76356. FIG. 10 shows the structure of such transistors.
With reference to FIG. 10, a TFT is configured with a substrate 101, a channel layer 104 disposed on the substrate 101, a gate-insulating film 103 disposed on the channel layer 104, a gate electrode 102 disposed on the gate-insulating film 103, and a drain 105 and a source 106 formed in the channel layer 104. The drain 105 and the source 106 are formed by decreasing the resistance of the channel layer 104 at both sides of the gate-insulating film 103 being in contact with the channel layer 104.
The structure of the transistor shown in FIG. 10 does not have unnecessary resistance between the drain 105 and the channel layer 104 and between the source 106 and the channel layer 104, unlike the structures shown in FIGS. 8 and 9. The drain 105 and the source 106 are in direct contact with the interface between the channel layer 104 and the gate-insulating film 103. Furthermore, no gaps and distortion in shape occur in the interface between the channel layer 104 and the gate-insulating film 103, and thus the favorable interface properties can be maintained. In addition, the interface between the channel layer 104 and the gate-insulating film 103 is not corroded with the etching liquid, gas, or plasma, or the resist and organic solvent, and thereby the drain 105 and the source 106 can be formed without degradation of the favorable interface properties. Thus, in the structure shown in FIG. 10, the problems in the structures of the transistors shown in FIGS. 8 and 9 can be solved.
However, when a transistor having a structure shown in FIG. 10 is fabricated according to the technology disclosed in Japanese Patent Laid-Open No. 2002-76356, part of the channel layer is formed by doping such as solid-phase diffusion of an impurity, ion implantation, or plasma doping. Therefore, an ion implantation apparatus having an accelerator or a plasma device for doping is necessary. In addition, a heating process of equalizing the doping is necessarily conducted. When an oxide semiconductor is used as the channel layer, heating at a high temperature must be conducted for a long period of time because the diffusion coefficient of an impurity in an oxide is lower than that in silicon.
As mentioned above, such use of large apparatuses disadvantageously causes an increase in the cost. In addition, the oxide semiconductor is crystallized or recrystallized by the treatment at a high temperature, and thereby the surface shape of the oxide-semiconductor channel layer is deformed. Furthermore, reaction and diffusion occur between the oxide-semiconductor channel layer and the gate-insulating film, and thereby the interface between the channel layer and the gate-insulating film is degraded. Even if these problems would not occur, the heating at a high temperature for a long period of time is highly troublesome in transistor manufacturing and increases the manufacturing cost.
The present invention provides high-quality and high-performance devices at low costs by solving the above-mentioned problems in methods for manufacturing oxide-semiconductor devices such as field-effect transistors (FETs) using oxide-semiconductors as channels.